About the High Performance Computing Center of the University of Tartu

The High Performance Computing Center is a consortium of UT and it's purpose is to build and develop  the necessary infrastructure for scientific computing. It also manages and coordinates the use of said computing equipment. This computing resource is open for use to any research groups inside the university. Users from other Estonian science- and research institutions are also welcome.

The computing center is run by a committee and a manager. Members of the committee:

Intel Xeon Phi

Introduction to Xeon Phi

Xeon Phi or the Intel Many Integrated Core Architecture (Intel MIC) is a coprocessor computer architecture developed by Intel.

Intel Parallel Studio XE 2015

Intel® Parallel Studio XE 2015 consists of the following components:

Intel Cluster Studio XE 2013

Intel® Cluster Studio XE consists of the following components:

Job limits and queueing

Every job submitted to the scheduling system is subject to some kind of resource limits. This is necessary in order to prevent for example one user from taking up the entire cluster for an indefinite time period. In general we try to specify the limits based on the following assumptions:

Rocket cluster

About the cluster

The main part of the Rocket cluster consists of 135 compute nodes (called stage1 - stage135), 4 compute nodes with Intel Xeon Phi accelerator cards (called booster1 - booster4) and a headnode rocket.hpc.ut.ee.

Using "Silinder"

The silinder.hpc.ut.ee machine is meant to be used for problems requiring large amounts of memory.

Silinder's hardware:

  • 4 Intel Xeon X7550 CPU-d @ 2Ghz (32 cores in total)
  • 512GB RAM
  • 1TB storage

This machine is used just like the rest of the cluster, by submitting your jobs to the scheduling and queueing system. The only difference is that the resource manager on silinder.hpc.ut.ee is completely separate from the rest of the cluster and only manages resources on that particular machine.

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